1. Field of the Invention
This invention relates to electronic systems, and more particularly, the optimization and margin characterization of input/output lines.
2. Description of the Related Art
In the design and operation of high-speed digital systems, such as computer systems, skew occurring on signal lines is one important consideration. Skew may be defined as timing differences between signals due to various propagation delays. In order for data to be received at the correct value, it must be latched into a receiver at a certain time, at a certain voltage level. One timing difference of critical importance in digital systems is the timing difference that may exist between clock signals and data signals. These timing differences may occur for a number of reasons, such as varying signal line lengths, electrical characteristics of individual signal lines, and so on.
FIG. 1 is a drawing of an exemplary printed circuit board (PCB) having two integrated circuits (IC) coupled by a plurality of signal lines. PCB 5 includes IC's 10A and 10B. IC's 10A and 10A include data ports 12A and 12B, respectively. Data ports 12A and 12B are coupled to each other by a plurality of signal lines 15. Due to space limitations, signal lines 15 must be routed in the manner shown in the drawing. Due to this routing, some of signal lines 15 are significantly longer than others. Signals traveling along the longer signal lines may take longer to travel between the two data ports. In some cases, data transfers between the two ports may be required to be performed in parallel. Thus, the receiving data port must latch the data from all lines simultaneously. Thus, since the data must be latched simultaneously, the timing differences between the various signal lines becomes critical.
Calibrating I/O lines may include tuning voltage levels and timing delays so that a signal is sampled within an enclosed area of an eye pattern. An exemplary eye pattern is shown in FIG. 2. The eye pattern may be plotted as an area on a graph of voltage vs. time (setup time, hold time), with voltage on the vertical axis and time on the horizontal axis. The contiguous enclosed regions within the lines may represent the area in which data may be accurately latched into a receiver. Ideally, signal sampling will occur in the middle of the eye pattern, at a point where both the voltage level and the setup/hold time allow for a large margin of operation for these parameters. Optimizing the reception of such signal transmissions may include tuning the voltage offset levels and tuning delay times as to ensure that the signal arrives at the receiver at a voltage level of sufficient magnitude. Optimizing the reception may also include adjusting a timing delay for sampling the signal in order to ensure that the setup and hold times are sufficient to properly receive the data. This may be performed for clock synchronous or source synchronous systems, but may have a greater impact on source synchronous systems, which typically operate at higher clock frequencies and with smaller margins of operation.
Sampling at points other than the middle of the eye pattern may reduce the margin of operation for either the voltage or setup/hold time. For example, if the voltage at which the signal is sampled is at a level that is above the midpoint, the margin of operation of the delay time may be less. Similarly, if a signal is sampled at a setup/hold time that is at a point other than the midpoint, the margin of operation of the voltage may be less. Furthermore, changing the voltage levels may affect the setup/hold times, and changes to the setup/hold times may affect the voltage levels. Thus, tuning both the voltage levels and delay times may involve the balancing of potentially conflicting requirements.
The calibrating of I/O lines may often times be performed during the design verification phase for an electronic system. This may involve a manual process of setting the voltage and timing delays for signal transmissions that occur in the system. Typically, these parameters, once set, do not change throughout the operating life of the system. Thus, changes in the operating conditions of the system may result in lower margins of operation for the voltage levels and/or the timing delays.